This page is maintained by David Lee ( dave@livstones.freeserve.co.uk ).
At present this report is NOT web friendly, having been converted by brute force from the LaTeX source. It is also not complete in length, and ommits all the figures. Please email me for a full copy.
Last modified on Monday, October 18, 1999

Coventry University
Electrical and Electronic Engineering
Composite Audio Amplifier

Project Report
by
David Lee
Under the supervision of
Dr. Mike Kondrat

Contents

1  Introduction
    1.1  Project brief
    1.2  Overview
    1.3  Literature review
        1.3.1  Class D Amplifiers
        1.3.2  Composite Amplifiers
2  System Design
    2.1  Analysis of Class D stage
        2.1.1  Bandwidth of Class D stage
    2.2  Power losses of Class A stage
    2.3  System Simulation
        2.3.1  Single pole filter with hysteresis control
        2.3.2  SIMULINK control parameters
        2.3.3  SIMULINK results for simple system
        2.3.4  Multipole filter
            Pulse Width Modulation for a Three pole filter
            Conclusion for multipole filters
        2.3.5  Biphase switching
            Ripple current magnitude
            Conclusion for Biphase switching
    2.4  Other system variations and refinements
3  Circuit Construction
    3.1  Component Selection
    3.2  Harris Driver PCB
        3.2.1  Circuit test
    3.3  Final PCB
        3.3.1  Class A stage
            Circuit features of Class A stage
            Circuit response of Class A stage
        3.3.2  Class D stage
            Circuit features of Class D stage
            Circuit response of Class D stage
4  Experimental Results
    4.1  Initial testing of the composite amplifier
        4.1.1  Amplifier measurements
    4.2  Test measurements and Equipment for audio power amplifiers
        4.2.1  Test procedures and definition of terms
            Frequency response
            Noise output
            Total Harmonic Distortion
            Intermodulation distortion
            Full power
    4.3  Test Results
        4.3.1  Frequency response
        4.3.2  Total Harmonic Distortion
        4.3.3  Efficiency
        4.3.4  Variation in supply voltage
        4.3.5  Maximum power
        4.3.6  Audio test
5  Discussion, Conclusion, and Further Work
    5.1  Discussion
        5.1.1  Simulation
            Comparison of experimental and simulated results
        5.1.2  University of Vienna
        5.1.3  Harris MOSFET driver
        5.1.4  Test procedures, and Circuit development
    5.2  Conclusions
    5.3  Further Work
        5.3.1  Development of the current design
            Speed of hysteresis control
            Value of inductor
            Power supplies
            Single rail supply
            Efficiency
        5.3.2  Simulation techniques
        5.3.3  Pulse Width Modulation control
        5.3.4  Biphase circuit
A  Distortion calculation
B  Equipment used

List of Figures

These are currently not available in this HTML version     1.1  System Block Diagram

    2.1  Class D hysteresis control waveforms
    2.2  Class A current waveforms
    2.3  SIMULINK model of simple system
    2.4  Relay characteristics variation with simulation method
    2.5  Filter voltages, Filter current, and Ripple current
    2.6  3rd order 4 ohm filter
    2.7  Unstable nature of hysteresis control with 3 pole filter
    2.8  SPICE confirmation of 3 pole filter result
    2.9  SIMULINK arrangement for PWM with 3 pole filter
    2.10  Semi stable nature of PWM control with 3 pole filter
    2.11  Biphase switching current waveforms - ideal inductors
    2.12  Biphase switching current waveforms - resistive inductors
    2.13  Biphase switching block diagram
    2.14  Biphase ripple current
    2.15  Equivalent circuit for 8 ohm loudspeaker

    3.1  Circuit diagram for Class A circuit section
    3.2  Circuit diagram for Class D circuit section

    4.1  Amplifier at 5kHz, with 12 ohm load and 15V rails
    4.2  Square wave response, showing current slew rate.
    4.3  Noise onto power supplies, with 20V p-p square wave into 7.4 ohms
    4.4  Current and voltage output ripple, with no input
    4.5  Current and voltage ripple, after snubber network added
    4.6  Current and voltage ripple, at 260kHz, into 7.4 ohms with 18V rails
    4.7  Class A current variation during 11Hz 28V p-p output wave
    4.8  Distortion, believed to be due to Class A amplifier overheating
    4.9  Frequency response
    4.10  Harmonic distortion

Acknowledgement

Input received from supervisor

Almost all student projects depend on the project supervisor for ideas and experience, and this one is no exception. I would especially like to thank Dr Kondrat for his assistance in the following areas.

The only unproductive suggestion I received from Dr Kondrat was the use of the opto-isolator for level shifting, but the failure to check the data sheet for speed of operation is my responsibility, as are all the minor circuit details.

Chapter 1
Introduction

Various designs have been proposed for power amplifiers, but, for the audio field, the low level of distortion offered by the standard Class A, or Class AB, output stages has left few other serious contenders. They do, however, lack efficiency. Class D amplifiers offer high efficiency, but traditionally have had poor performance. Recently work has been done on a composite design, using a low powered Class A stage to give quality, with a Class D stage providing the power and efficiency. The Class D output is a slave to the master Class A output, which implies, firstly, that the Class D stage can not function by itself, and secondly, the possibility of instability if it assists too much. This project aims to investigate this configuration, and build an amplifier on this principle

1.1  Project brief

1.2  Overview

A Class D amplifier is characterised by the output transistors being switched at a frequency above that of the required bandwidth, and the resultant output then low pass filtered. This results in very low power losses in the output transistors (ideally zero). However, the output does usually show relatively poor signal quality. However, work has recently been done on combining this arrangement with a Class A output stage to improve the quality, whilst still maintaining efficiency.

Figure

Figure 1.1: System Block Diagram

Figure 1.1 shows the configuration normally used. A Class A amplifier causes a current to flow through the sense resistor, which is measured. This current signal is used to control the Class D driver stage, causing a current iL to flow through the inductor. This current, which then flows into the load, should be most of the required current, resulting in the Class A amplifier providing only a minimal correcting current, which will include the ripple current component of iL

The efficiency of this arrangement is maximised by reducing the power losses, present in the non-ideal switching of the Class D stage, and the Class A output, and the control circuitry. Of these, the Class A output losses are likely to dominate, so should be minimised to improve efficiency. Simple theory gives the maximum efficiency of a single ended Class A output as 25%, with a quiescent output device current of the peak load current. It is therefore important to minimise the current supplied by the Class A stage.

The expression `Class A' within this report is intended in the widest sense, that is to also include Class B and Class A-B output stages. Strictly, Class A is defined by the output devices remaining in the active region for all of a complete cycle of a sine wave input.

1.3  Literature review

1.3.1  Class D Amplifiers

The Class D amplifiers concept dates back to , with the general wisdom being that they could not offer sufficient quality for audio systems. However, as the technology is similar to that for switch mode power supplies, for which the switching frequency has been steadily increasing, the performance of Class D amplifiers have steadily improved. Recently, according to information on the Internet, there has been several Class D audio amplifiers introduced, from LinFinity, ST Microelectronics, and Harris Semiconductors. National Semiconductors and Texas Instruments are also known to be active in this area1, and a recent edition of the trade magazine Electronic Design featured an article on Class D amplifiers []. Harris appears to be one of the main players, and is licensing 220W full bandwidth designs to Alpine and Goldpeak [].

1.3.2  Composite Amplifiers

A paper aiming to comprehensively cover all useful combinations of composite amplifiers was published by . However, this work does not seem to have been followed up by anyone. The Quad 405 current dumping amplifier of 1975 could be considered a composite amplifier, but the most useful means of analysing it seems to have been as an output bridge circuit [][]. Another composite design is the Class S configuration of . The configuration used in this project was that suggested by , which covers the design of a 1kW amplifier of the type outlined above. They intended to publish the experimental results when obtained, but I have not yet seen any such paper. tried an alternative configuration, and later, along with Jung, reported on the same configuration as Ertl[], but added very little new material.

Chapter 2
System Design

2.1  Analysis of Class D stage

To obtain efficiency, the output current from the Class A stage must be minimised, allowing minimised quiescent currents and power losses. Therefore, the Class D stage must closely follow the signal. A simple analysis of the Class D performance is as follows.

Figure  1.8mm
Picture Omitted

Figure 2.1: Class D hysteresis control waveforms

Consider supplies of ±U supplying a load RL through an inductor L. Let the peak to peak ripple current in the load be limited by the control system to DI (Hysteresis control), as shown in figure 2.1. Then, assuming the ripple on the output voltage u is small compared to U, and a linear approximation for the inductor current, for a duty cycle of 0.5

L di
dt
=
U
L DI
T
2
=
U
Thus
fmax = 1
T
 = U
2L DI
(2.1)
This is the maximum frequency under hysteresis control, as can be shown by considering the more general case of a duty cycle d, which will produce an average output voltage u. A modulation index, m, given by m = [u/U] is useful in normalising the voltages and giving simpler expressions. m will always be within the range -1 £ m £ 1.

d
=
1+ u
U
2
 = 1+m
2
L DI
dT
=
U-u = U(1-m) (Charging)
f = 1
T
=
U(1-m) d
L DI
f
=
U(1-m) (1+m)
2L DI
 = fmax(1-m2)
which shows the maximum switching frequency occurs for zero output voltage (m = 0). The ripple current magnitude is given by
DI = U T (1-m2)
2L
(2.2)
which is true for hysteresis or PWM control.

2.1.1  Bandwidth of Class D stage

The RL on the output of the Class D stage acts as a low pass filter on the switched waveform, with a 3dB point at f = [R/(2 pL)] , but there is also a slew rate limitation as the available current to the load is limited. The limiting value is dependant on any existing output voltage. Consider the system stable at a modulation level m, when a step positive going edge arrives. The Class A amplifier (considered ideal) follows it, and the resulting extra current causes an immediate switch in the Class D driver circuit to deliver current from the positive rail. Then

L di
dt
=
U-u = U(1-m)
The power bandwidth of the Class D stage is when this rate of current change can not keep up with the maximum current change required through the load when a sinusoid of maximum allowed amplitude is applied. However, the maximum allowed size of the step considered above would be U-u to avoid overload. Therefore, the power bandwidth, wP is given by

wP U(1-m)
=
R
L
 U (1-m)
fP
=
wP
2p
 = R
2 pL
Therefore, the small signal 3dB point, and the power bandwidth limit occur at the same frequency, which is independent of quiescent output level.

2.2  Power losses of Class A stage

Figure  2.00mm
Picture Omitted

Figure 2.2: Class A current waveforms

For the Class A stage, the current demand is symmetrical and peaks at ±DI / 2 , with the voltage across the top transistor being U-u and across the bottom transistor being U+u. The waveforms are shown in figure 2.2, and the total power losses can be assessed by considering the energy per cycle, split into three parts as follows, with Etop and Ebottom obtained from the geometry of the waveforms shown in figure 2.2

EQ
=
2U IQ T quiescent current
Etop
=
(U-u) DI T
8
 for current sourcing
Ebottom
=
(U+u) DI T
8
 for current sinking
Power = Etop+Ebottom+EQ
T
=
2U æ
ç
è 		IQ + DI
8
 ) ö
÷
ø
For full Class A operation, IQ > 0, while for Class B IQ = 0 . Therefore, for Class B
Power = 2U æ
ç
è 		0 + DI
8
 ) ö
÷
ø 		= DI U
4

The efficiency of an amplifier is usually taken for a sinusoid wave at the maximum undistorted output, which, for our composite amplifier, is a peak to peak voltage of 2U into a load of R. The power in the load is therefore U2/2R. Assuming the only losses are as detailed above, and with efficiency, h, being defined as power in load divided by total power supplied, we obtain:

h
=
2U2
2U2+DI U R
 = 2U
2U+DI R
 for a Class B
(2.3)
Therefore, for 80% efficiency, DI < U/2R using a Class B stage, demonstrating the need to minimise the ripple current.

As a comparison, for a Class B amplifier by itself, the efficiency as calculated for a sinusoid waveform, not the triangular waveform used above, is a maximum of p/4 or 78.5%.

suggests several techniques to help, and two alternative ways were investigated - a multipole filter, and biphase switching.

Before these could be investigated, however, the problems of simulating the system required investigating.

2.3  System Simulation

Figure
Figure 2.3: SIMULINK model of simple system

System simulation allows various arrangements to be tried, and can confirm some design decisions. The SIMULINK (version 1.3c) extension to MATLAB was available for this work. However, to allow the output inductor to be replaced by a multipole filter, it was modelled as having two inputs, which are the voltages at each end of it, and one output, the current it feeds into the load. This easily allows modelling of stored charge on capacitors to ground in multipole filters, but does mean that a state space representation of the filter is required, as shown in figure 2.3

2.3.1  Single pole filter with hysteresis control

The block diagram of figure 2.3 shows the arrangement used. Included in this model are the following assumptions:

It can be predicted, using equation 2.1, that the maximum switching frequency should be 500kHz.

2.3.2  SIMULINK control parameters

FigureFigureFigure
Figure 2.4: Relay characteristics variation with simulation method
The ideal relay characteristics would be single vertical lines at - 1.2 and + 1.2, joining the horizontal lines at -24 and +24. The above plots show that SIMULINK does not accurately produce such results.

The results of the simulation of this system initially showed unexpected values at the input to the relay. The simulation control parameters were therefore investigated and found to be important. The parameters available were

Integration method. A choice of Linsim, Runge-Kutta 3, Runge-Kutta 5, Adams, Gear, Adams-Gear, and Euler
Minimum step size. Recommended value is 10-6
Maximum step size.
Tolerance. Recommended value between 0.1 and 10-6

The MATLAB documentation recommends LINSIM for linear systems with a few non-linear elements, and using EULER only to verify results.

A technique of plotting the response of the relay unit was adopted to ensure the results could be believed, and typical results from this are shown in figure 2.4. My understanding is that all of those plots, which were actually taken from simulating a biphase system, should show single vertical transitions at ±1.2, not the multiple transitions particularly visible in the run using Linsim integration with maximum step size set to 5 ×10-2. A factor of 106 scaling was applied to the reactive components in the model, to allow 1 time unit in the simulation to correspond to 1 microsecond.

The overall results are summarized in the following table, including the time taken for the simulation. The minimum step size was always 10-7, and the tolerance 10-3.

Method Maximum Step run time switch range
Linsim 1e-2 65 0.85 to 1.15
Adams 1e-2 40 0.8 to 1.15
Gear 1e-2 45 0.82 to 1.2
Adams-Gear 1e-2 45 0.8 to 1.2
Euler 1e-2 40 0.8 to 1.1
Euler 5e-3 80 1 to 1.12
Linsim 5e-3 140 0.94 to 1.07

Simulations were therefore done with the Linsim integration method, with a minimum step size of 10-7, a maximum step size of 0.03, and a tolerance of 10-3, later reduced to 10-4.

2.3.3  SIMULINK results for simple system

Figure
Figure 2.5: Filter voltages, Filter current, and Ripple current

Using the above parameters, the results of figure 2.5 were obtained. A step input occurs at 10 ms, with the output voltage switching from 0V to 12V. The zero volt switching frequency of 0.5MHz, as predicted above, and the slew rate of 1.2 A/ms can be clearly seen. The full power bandwidth of this arrangement is therefore 63kHz. However, the efficiency of the system is limited because the Class A stage must supply up to 1.2A. From equation 2.3 the efficiency would be about 83% for a Class B controlling amplifier. To improve this we must reduce the ripple current, which requires increasing either (or both) the switching frequency, or the inductance value, or changing the circuit configuration. Initially, attention was given to a higher order filter.

2.3.4  Multipole filter

Figure
Figure 2.6: 3rd order 4 ohm filter

Figure
Figure 2.7: Unstable nature of hysteresis control with 3 pole filter
The current waveform is increasing in magnitude.

Figure
Figure 2.8: SPICE confirmation of 3 pole filter result

A multipole filter was considered to reduce the switching frequency, or the ripple current. Construction of a second order filter was not considered worth investigating, as this would result in the Class A amplifier having a large capacitive load, which is well known to cause stability problems. Attention was therefore centred on a third order LCL filter, and for simplicity, values of L and C for a Butterworth response into a 4 ohm load were selected, as shown in figure 2.6, the corner frequency being 50 kHz. For inclusion in SIMULINK, this had to be modelled as state equations, which, using the physical variables vC,iL1,iL2 as the state variables, gave the equation

.
x
 
 = 0
1
1.06
-1
1.06
 -1
19
0
0 1
6.4
0
0 x +0
0 1
19
0 0
-1
6.4
 u